V_BLEND_SET_GLOBAL_ALPHA_REG (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

V_BLEND_SET_GLOBAL_ALPHA_REG (DISPLAY_PORT) Register Description

Register NameV_BLEND_SET_GLOBAL_ALPHA_REG
Offset Address0x000000A00C
Absolute Address 0x00FD4AA00C (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionTo set the global alpha

V_BLEND_SET_GLOBAL_ALPHA_REG (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:9razRead as zero0x0
VALUE 8:1rwNormal read/write0x08: 1: Global Alpha Value. 0: Transparent, 255: Opaque
EN 0rwNormal read/write0x0Global Alpha Enable