WDT_CLK_SEL (FPD_SLCR) Register Description
| Register Name | WDT_CLK_SEL |
|---|---|
| Offset Address | 0x0000000100 |
| Absolute Address | 0x00FD610100 (FPD_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | FPD SWDT clock source select (WDT) |
WDT_CLK_SEL (FPD_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | Trigger an address decode error interrupt. 0: Ignored 1: isr -> 1 |
| SELECT | 0 | rwNormal read/write | 0x0 | System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO) |