ZDMA_CH_CTRL1 (ZDMA) Register Description
| Register Name | ZDMA_CH_CTRL1 |
|---|---|
| Offset Address | 0x0000000114 |
| Absolute Address |
0x00FFA80114 (ADMA_CH0) 0x00FFA90114 (ADMA_CH1) 0x00FFAA0114 (ADMA_CH2) 0x00FFAB0114 (ADMA_CH3) 0x00FFAC0114 (ADMA_CH4) 0x00FFAD0114 (ADMA_CH5) 0x00FFAE0114 (ADMA_CH6) 0x00FFAF0114 (ADMA_CH7) 0x00FD500114 (GDMA_CH0) 0x00FD510114 (GDMA_CH1) 0x00FD520114 (GDMA_CH2) 0x00FD530114 (GDMA_CH3) 0x00FD540114 (GDMA_CH4) 0x00FD550114 (GDMA_CH5) 0x00FD560114 (GDMA_CH6) 0x00FD570114 (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x000003FF |
| Description | Channel Control Register 1 |
ZDMA_CH_CTRL1 (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:10 | razRead as zero | 0x0 | Reserved for future use |
| DST_ISSUE | 9:5 | rwNormal read/write | 0x1F | Outstanding transaction on DST 00000: One outstanding transactions 11111: 32 outstanding transactions This field must remain stable while DMA Channel is enabled |
| SRC_ISSUE | 4:0 | rwNormal read/write | 0x1F | Outstanding transaction on SRC 00000: One outstanding transactions 11111: 32 outstanding transactions This field must remain stable while DMA Channel is enabled |