ZDMA_CH_CTRL2 (ZDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ZDMA_CH_CTRL2 (ZDMA) Register Description

Register NameZDMA_CH_CTRL2
Offset Address0x0000000200
Absolute Address 0x00FFA80200 (ADMA_CH0)
0x00FFA90200 (ADMA_CH1)
0x00FFAA0200 (ADMA_CH2)
0x00FFAB0200 (ADMA_CH3)
0x00FFAC0200 (ADMA_CH4)
0x00FFAD0200 (ADMA_CH5)
0x00FFAE0200 (ADMA_CH6)
0x00FFAF0200 (ADMA_CH7)
0x00FD500200 (GDMA_CH0)
0x00FD510200 (GDMA_CH1)
0x00FD520200 (GDMA_CH2)
0x00FD530200 (GDMA_CH3)
0x00FD540200 (GDMA_CH4)
0x00FD550200 (GDMA_CH5)
0x00FD560200 (GDMA_CH6)
0x00FD570200 (GDMA_CH7)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionzDMA Control Register 2

ZDMA_CH_CTRL2 (ZDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1razRead as zero0x0Reserved for future use
EN 0rwNormal read/write0x0Channel is enabled.
SW sets this 1 to trigger. If DMA channel is in pause and this bit is cleared by software then DMA channel goes to disable state when SW set CONT bit.
HW clears this flag after finishing DMA operation.