ZDMA_CH_DATA_ATTR (ZDMA) Register Description
| Register Name | ZDMA_CH_DATA_ATTR |
|---|---|
| Offset Address | 0x0000000120 |
| Absolute Address |
0x00FFA80120 (ADMA_CH0) 0x00FFA90120 (ADMA_CH1) 0x00FFAA0120 (ADMA_CH2) 0x00FFAB0120 (ADMA_CH3) 0x00FFAC0120 (ADMA_CH4) 0x00FFAD0120 (ADMA_CH5) 0x00FFAE0120 (ADMA_CH6) 0x00FFAF0120 (ADMA_CH7) 0x00FD500120 (GDMA_CH0) 0x00FD510120 (GDMA_CH1) 0x00FD520120 (GDMA_CH2) 0x00FD530120 (GDMA_CH3) 0x00FD540120 (GDMA_CH4) 0x00FD550120 (GDMA_CH5) 0x00FD560120 (GDMA_CH6) 0x00FD570120 (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x0483D20F |
| Description | Channel DATA AXI parameter Register |
This register must remain stable while DMA Channel is enabled
ZDMA_CH_DATA_ATTR (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:28 | razRead as zero | 0x0 | reserved |
| ARBURST | 27:26 | rwNormal read/write | 0x1 | Burst Type for SRC AXI transaction 00: Fixed burst 01: Incremental burst 1x: reserved |
| ARCACHE | 25:22 | rwNormal read/write | 0x2 | AXI cache bits for Data read. Default non-cacheable, non-bufferable. |
| ARQOS | 21:18 | rwNormal read/write | 0x0 | Configurable QoS bits for AXI Data read |
| ARLEN | 17:14 | rwNormal read/write | 0xF | AXI Length for Data Reads (power of 2 value): 0: 1 data beat 1: 2 2: 4 3: 8 4 or greater: 16 data beats |
| AWBURST | 13:12 | rwNormal read/write | 0x1 | Burst Type for DST AXI transaction 00: Fixed burst 01: Incremental burst 1x: reserved |
| AWCACHE | 11:8 | rwNormal read/write | 0x2 | AXI cache bits for Data write. Default non-cacheable, non-bufferable. |
| AWQOS | 7:4 | rwNormal read/write | 0x0 | Configurable QoS bits for AXI Data write |
| AWLEN | 3:0 | rwNormal read/write | 0xF | AXI Length for Data Writes (power of 2 value): 0: 1 data beat 1: 2 2: 4 3: 8 4 or greater: 16 data beats |