ZDMA_CH_DSCR_ATTR (ZDMA) Register Description
| Register Name | ZDMA_CH_DSCR_ATTR |
|---|---|
| Offset Address | 0x0000000124 |
| Absolute Address |
0x00FFA80124 (ADMA_CH0) 0x00FFA90124 (ADMA_CH1) 0x00FFAA0124 (ADMA_CH2) 0x00FFAB0124 (ADMA_CH3) 0x00FFAC0124 (ADMA_CH4) 0x00FFAD0124 (ADMA_CH5) 0x00FFAE0124 (ADMA_CH6) 0x00FFAF0124 (ADMA_CH7) 0x00FD500124 (GDMA_CH0) 0x00FD510124 (GDMA_CH1) 0x00FD520124 (GDMA_CH2) 0x00FD530124 (GDMA_CH3) 0x00FD540124 (GDMA_CH4) 0x00FD550124 (GDMA_CH5) 0x00FD560124 (GDMA_CH6) 0x00FD570124 (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Channel DSCR AXI parameter Register |
This register must remain stable while DMA Channel is enabled
ZDMA_CH_DSCR_ATTR (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:9 | razRead as zero | 0x0 | Reserved for future use |
| AXCOHRNT | 8 | rwNormal read/write | 0x0 | This field is only valid for LPD DMA. FPD DMA does not support coherency at descriptor and data. 0: AXI transactions generated for the descriptor read are marked Non-coherent. 1: AXI transactions generated for the descriptor read are marked coherent. |
| AXCACHE | 7:4 | rwNormal read/write | 0x0 | AXI cache bit used for DSCR fetch (both on SRC and DST Side). |
| AXQOS | 3:0 | rwNormal read/write | 0x0 | QoS bit used for DSCR fetch (both on SRC and DST side). |