ZDMA_CH_DST_DSCR_WORD0 (ZDMA) Register Description
| Register Name | ZDMA_CH_DST_DSCR_WORD0 |
|---|---|
| Offset Address | 0x0000000138 |
| Absolute Address |
0x00FFA80138 (ADMA_CH0) 0x00FFA90138 (ADMA_CH1) 0x00FFAA0138 (ADMA_CH2) 0x00FFAB0138 (ADMA_CH3) 0x00FFAC0138 (ADMA_CH4) 0x00FFAD0138 (ADMA_CH5) 0x00FFAE0138 (ADMA_CH6) 0x00FFAF0138 (ADMA_CH7) 0x00FD500138 (GDMA_CH0) 0x00FD510138 (GDMA_CH1) 0x00FD520138 (GDMA_CH2) 0x00FD530138 (GDMA_CH3) 0x00FD540138 (GDMA_CH4) 0x00FD550138 (GDMA_CH5) 0x00FD560138 (GDMA_CH6) 0x00FD570138 (GDMA_CH7) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | DST DSCR Word 0 |
This register must remain stable while DMA Channel is enabled
ZDMA_CH_DST_DSCR_WORD0 (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| LSB | 31:0 | rwNormal read/write | 0x0 | Lower 32-bits of Address |