ZDMA_CH_DST_DSCR_WORD1 (ZDMA) Register Description
| Register Name | ZDMA_CH_DST_DSCR_WORD1 |
|---|---|
| Offset Address | 0x000000013C |
| Absolute Address |
0x00FFA8013C (ADMA_CH0) 0x00FFA9013C (ADMA_CH1) 0x00FFAA013C (ADMA_CH2) 0x00FFAB013C (ADMA_CH3) 0x00FFAC013C (ADMA_CH4) 0x00FFAD013C (ADMA_CH5) 0x00FFAE013C (ADMA_CH6) 0x00FFAF013C (ADMA_CH7) 0x00FD50013C (GDMA_CH0) 0x00FD51013C (GDMA_CH1) 0x00FD52013C (GDMA_CH2) 0x00FD53013C (GDMA_CH3) 0x00FD54013C (GDMA_CH4) 0x00FD55013C (GDMA_CH5) 0x00FD56013C (GDMA_CH6) 0x00FD57013C (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DST DSCR Word 1 |
This register must remain stable while DMA Channel is enabled
ZDMA_CH_DST_DSCR_WORD1 (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:17 | razRead as zero | 0x0 | Reserved for future use |
| MSB | 16:0 | rwNormal read/write | 0x0 | Upper 12-bits of Address |