ZDMA_CH_DST_DSCR_WORD3 (ZDMA) Register Description
| Register Name | ZDMA_CH_DST_DSCR_WORD3 |
|---|---|
| Offset Address | 0x0000000144 |
| Absolute Address |
0x00FFA80144 (ADMA_CH0) 0x00FFA90144 (ADMA_CH1) 0x00FFAA0144 (ADMA_CH2) 0x00FFAB0144 (ADMA_CH3) 0x00FFAC0144 (ADMA_CH4) 0x00FFAD0144 (ADMA_CH5) 0x00FFAE0144 (ADMA_CH6) 0x00FFAF0144 (ADMA_CH7) 0x00FD500144 (GDMA_CH0) 0x00FD510144 (GDMA_CH1) 0x00FD520144 (GDMA_CH2) 0x00FD530144 (GDMA_CH3) 0x00FD540144 (GDMA_CH4) 0x00FD550144 (GDMA_CH5) 0x00FD560144 (GDMA_CH6) 0x00FD570144 (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DST DSCR Word 3 |
This register must remain stable while DMA Channel is enabled
ZDMA_CH_DST_DSCR_WORD3 (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:3 | razRead as zero | 0x0 | Reserved for future use |
| INTR | 2 | rwNormal read/write | 0x0 | 0: Completion interrupt is not required. 1: Interrupt is set at the completion of this element. Completion indicates data has been written to the memory and BRESP has been received. |
| Reserved | 1 | razRead as zero | 0x0 | Reserved for future use |
| COHRNT | 0 | rwNormal read/write | 0x0 | This field is only valid for LPD DMA. FPD DMA does not support coherency at descriptor and data. 0: AXI transactions generated to process the descriptor payload are marked Non-coherent. 1: AXI transaction generated to process the descriptor payload are marked coherent. |