ZDMA_CH_IDS (ZDMA) Register Description
Register Name | ZDMA_CH_IDS |
---|---|
Offset Address | 0x000000010C |
Absolute Address |
0x00FFA8010C (ADMA_CH0) 0x00FFA9010C (ADMA_CH1) 0x00FFAA010C (ADMA_CH2) 0x00FFAB010C (ADMA_CH3) 0x00FFAC010C (ADMA_CH4) 0x00FFAD010C (ADMA_CH5) 0x00FFAE010C (ADMA_CH6) 0x00FFAF010C (ADMA_CH7) 0x00FD50010C (GDMA_CH0) 0x00FD51010C (GDMA_CH1) 0x00FD52010C (GDMA_CH2) 0x00FD53010C (GDMA_CH3) 0x00FD54010C (GDMA_CH4) 0x00FD55010C (GDMA_CH5) 0x00FD56010C (GDMA_CH6) 0x00FD57010C (GDMA_CH7) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
ZDMA_CH_IDS (ZDMA) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:12 | razRead as zero | 0x0 | Reserved for future use |
DMA_PAUSE | 11 | woWrite-only | 0x0 | Interrupt is set when DMA channel goes in pause state |
DMA_DONE | 10 | woWrite-only | 0x0 | Interrupt is set when DMA channel is done (with or without error) |
AXI_WR_DATA | 9 | woWrite-only | 0x0 | Interrupt is set when AXI Write Error occurred on write data channel |
AXI_RD_DATA | 8 | woWrite-only | 0x0 | Interrupt is set when AXI Read Error occurred on read data channel |
AXI_RD_DST_DSCR | 7 | woWrite-only | 0x0 | Interrupt is set when AXI Read Error occurred on DST DSCR fetch |
AXI_RD_SRC_DSCR | 6 | woWrite-only | 0x0 | Interrupt is set when AXI Read Error occurred on SRC DSCR fetch |
IRQ_DST_ACCT_ERR | 5 | woWrite-only | 0x0 | Interrupt is set when DST Interrupt account counter overflows; Interrupt account counter value is not valid if this interrupt is set |
IRQ_SRC_ACCT_ERR | 4 | woWrite-only | 0x0 | Interrupt is set when SRC Interrupt account counter overflows; Interrupt account counter value is not valid if this interrupt is set |
BYTE_CNT_OVRFL | 3 | woWrite-only | 0x0 | Interrupt is set when byte count counter overflow; Counter value is not valid if this interrupt is set |
DST_DSCR_DONE | 2 | woWrite-only | 0x0 | Interrupt is set at the completion of DST Descriptor element. Completion indicates data has been written to the memory and BRESP has been received. |
SRC_DSCR_DONE | 1 | woWrite-only | 0x0 | Interrupt is set at the completion of SRC Descriptor. Completion indicates data has been read, but it may be in DMA buffer (and not yet written to destination). |
INV_APB | 0 | woWrite-only | 0x0 | Interrupt is set when an APB register access occurs to an unimplemented space. |