ZDMA_CH_IMR (ZDMA) Register Description
| Register Name | ZDMA_CH_IMR |
|---|---|
| Offset Address | 0x0000000104 |
| Absolute Address |
0x00FFA80104 (ADMA_CH0) 0x00FFA90104 (ADMA_CH1) 0x00FFAA0104 (ADMA_CH2) 0x00FFAB0104 (ADMA_CH3) 0x00FFAC0104 (ADMA_CH4) 0x00FFAD0104 (ADMA_CH5) 0x00FFAE0104 (ADMA_CH6) 0x00FFAF0104 (ADMA_CH7) 0x00FD500104 (GDMA_CH0) 0x00FD510104 (GDMA_CH1) 0x00FD520104 (GDMA_CH2) 0x00FD530104 (GDMA_CH3) 0x00FD540104 (GDMA_CH4) 0x00FD550104 (GDMA_CH5) 0x00FD560104 (GDMA_CH6) 0x00FD570104 (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000FFF |
| Description | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
ZDMA_CH_IMR (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:12 | razRead as zero | 0x0 | Reserved for future use |
| DMA_PAUSE | 11 | roRead-only | 0x1 | Interrupt is set when DMA channel goes in pause state |
| DMA_DONE | 10 | roRead-only | 0x1 | Interrupt is set when DMA channel is done (with or without error) |
| AXI_WR_DATA | 9 | roRead-only | 0x1 | Interrupt is set when AXI Write Error occurred on write data channel |
| AXI_RD_DATA | 8 | roRead-only | 0x1 | Interrupt is set when AXI Read Error occurred on read data channel |
| AXI_RD_DST_DSCR | 7 | roRead-only | 0x1 | Interrupt is set when AXI Read Error occurred on DST DSCR fetch |
| AXI_RD_SRC_DSCR | 6 | roRead-only | 0x1 | Interrupt is set when AXI Read Error occurred on SRC DSCR fetch |
| IRQ_DST_ACCT_ERR | 5 | roRead-only | 0x1 | Interrupt is set when DST Interrupt account counter overflows; Interrupt account counter value is not valid if this interrupt is set |
| IRQ_SRC_ACCT_ERR | 4 | roRead-only | 0x1 | Interrupt is set when SRC Interrupt account counter overflows; Interrupt account counter value is not valid if this interrupt is set |
| BYTE_CNT_OVRFL | 3 | roRead-only | 0x1 | Interrupt is set when byte count counter overflow; Counter value is not valid if this interrupt is set |
| DST_DSCR_DONE | 2 | roRead-only | 0x1 | Interrupt is set at the completion of DST Descriptor element. Completion indicates data has been written to the memory and BRESP has been received. |
| SRC_DSCR_DONE | 1 | roRead-only | 0x1 | Interrupt is set at the completion of SRC Descriptor. Completion indicates data has been read, but it may be in DMA buffer (and not yet written to destination). |
| INV_APB | 0 | roRead-only | 0x1 | Interrupt is set when an APB register access occurs to an unimplemented space |