ZDMA_CH_RATE_CTRL (ZDMA) Register Description
| Register Name | ZDMA_CH_RATE_CTRL |
|---|---|
| Offset Address | 0x000000018C |
| Absolute Address |
0x00FFA8018C (ADMA_CH0) 0x00FFA9018C (ADMA_CH1) 0x00FFAA018C (ADMA_CH2) 0x00FFAB018C (ADMA_CH3) 0x00FFAC018C (ADMA_CH4) 0x00FFAD018C (ADMA_CH5) 0x00FFAE018C (ADMA_CH6) 0x00FFAF018C (ADMA_CH7) 0x00FD50018C (GDMA_CH0) 0x00FD51018C (GDMA_CH1) 0x00FD52018C (GDMA_CH2) 0x00FD53018C (GDMA_CH3) 0x00FD54018C (GDMA_CH4) 0x00FD55018C (GDMA_CH5) 0x00FD56018C (GDMA_CH6) 0x00FD57018C (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Rate Control Count Register |
This register must remain stable while DMA Channel is enabled
ZDMA_CH_RATE_CTRL (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:12 | razRead as zero | 0x0 | Reserved for future use |
| CNT | 11:0 | rwNormal read/write | 0x0 | Scheduling interval for SRC AXI transaction, only used if rate control is enabled in control register |