ZDMA_CH_SRC_DSCR_WORD2 (ZDMA) Register Description
| Register Name | ZDMA_CH_SRC_DSCR_WORD2 |
|---|---|
| Offset Address | 0x0000000130 |
| Absolute Address |
0x00FFA80130 (ADMA_CH0) 0x00FFA90130 (ADMA_CH1) 0x00FFAA0130 (ADMA_CH2) 0x00FFAB0130 (ADMA_CH3) 0x00FFAC0130 (ADMA_CH4) 0x00FFAD0130 (ADMA_CH5) 0x00FFAE0130 (ADMA_CH6) 0x00FFAF0130 (ADMA_CH7) 0x00FD500130 (GDMA_CH0) 0x00FD510130 (GDMA_CH1) 0x00FD520130 (GDMA_CH2) 0x00FD530130 (GDMA_CH3) 0x00FD540130 (GDMA_CH4) 0x00FD550130 (GDMA_CH5) 0x00FD560130 (GDMA_CH6) 0x00FD570130 (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | SRC DSCR Word 2 |
This register must remain stable while DMA Channel is enabled
ZDMA_CH_SRC_DSCR_WORD2 (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:30 | razRead as zero | 0x0 | Reserved for future use |
| SIZE | 29:0 | rwNormal read/write | 0x0 | Buffer size in bytes (1G=2^30) |