ZDMA_CH_SRC_START_MSB (ZDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ZDMA_CH_SRC_START_MSB (ZDMA) Register Description

Register NameZDMA_CH_SRC_START_MSB
Offset Address0x000000015C
Absolute Address 0x00FFA8015C (ADMA_CH0)
0x00FFA9015C (ADMA_CH1)
0x00FFAA015C (ADMA_CH2)
0x00FFAB015C (ADMA_CH3)
0x00FFAC015C (ADMA_CH4)
0x00FFAD015C (ADMA_CH5)
0x00FFAE015C (ADMA_CH6)
0x00FFAF015C (ADMA_CH7)
0x00FD50015C (GDMA_CH0)
0x00FD51015C (GDMA_CH1)
0x00FD52015C (GDMA_CH2)
0x00FD53015C (GDMA_CH3)
0x00FD54015C (GDMA_CH4)
0x00FD55015C (GDMA_CH5)
0x00FD56015C (GDMA_CH6)
0x00FD57015C (GDMA_CH7)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSRC DSCR Start Address MSB Register

ZDMA_CH_SRC_START_MSB (ZDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:17razRead as zero0x0Reserved for future use
ADDR16:0rwNormal read/write0x0Start Address MSB register for SRC descriptor fetch.