ZDMA_CH_STATUS (ZDMA) Register Description
| Register Name | ZDMA_CH_STATUS |
|---|---|
| Offset Address | 0x000000011C |
| Absolute Address |
0x00FFA8011C (ADMA_CH0) 0x00FFA9011C (ADMA_CH1) 0x00FFAA011C (ADMA_CH2) 0x00FFAB011C (ADMA_CH3) 0x00FFAC011C (ADMA_CH4) 0x00FFAD011C (ADMA_CH5) 0x00FFAE011C (ADMA_CH6) 0x00FFAF011C (ADMA_CH7) 0x00FD50011C (GDMA_CH0) 0x00FD51011C (GDMA_CH1) 0x00FD52011C (GDMA_CH2) 0x00FD53011C (GDMA_CH3) 0x00FD54011C (GDMA_CH4) 0x00FD55011C (GDMA_CH5) 0x00FD56011C (GDMA_CH6) 0x00FD57011C (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Channel Status Register |
ZDMA_CH_STATUS (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | razRead as zero | 0x0 | Reserved for future use |
| STATE | 1:0 | roRead-only | 0x0 | 00: Done with no error (as a result Enable bit is cleared by HW) 01: paused with no error (as a result Enable bit remains set). 10: DMA is busy transferring 11: DMA done with error (error condition captured in other registers) This bit is cleared by HW when Enable or Unpause is set to 1. |