ZQ0OR1 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ZQ0OR1 (DDR_PHY) Register Description

Register NameZQ0OR1
Offset Address0x0000000698
Absolute Address 0x00FD080698 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionZQ 0 Impedance Control Override Data Register 1

ZQ0OR1 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:26roRead-only0x0Reserved. Return zeros on reads.
ZDATA_PU_ODT_OVRD25:16rwNormal read/write0x0Override value for the pull-up output impedance and is controlled
by ZQ0PR0.DRV_PU_ZDEN
Reserved15:10roRead-only0x0Reserved. Return zeros on reads.
ZDATA_PD_ODT_OVRD 9:0rwNormal read/write0x0Override value for the pull-down output impedance and is
controlled by ZQ0PR0.DRV_PD_ZDEN