ZQ0PR0 (DDR_PHY) Register Description
| Register Name | ZQ0PR0 |
|---|---|
| Offset Address | 0x0000000684 |
| Absolute Address | 0x00FD080684 (DDR_PHY) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x000077BB |
| Description | ZQ 0 Impedance Control Program Register 0 |
ZQ0PR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PD_DRV_ZDEN | 31 | rwNormal read/write | 0x0 | Pulldown Drive strength ZCTRL over-ride Enable: When this bit is set, it allows users to directly drive the drive strength bits of the impedance control using the data programmed in the ZQnOR.ZDATA field. Otherwise, the ZCTRL is generated automatically by the impedance control logic. |
| PU_DRV_ZDEN | 30 | rwNormal read/write | 0x0 | Pullup Drive strength ZCTRL over-ride Enable: When this bit is set, it allows users to directly drive the drive strength bits of the impedance control using the data programmed in the ZQnOR.ZDATA field. Otherwise, the ZCTRL is generated automatically by the impedance control logic. |
| PD_ODT_ZDEN | 29 | rwNormal read/write | 0x0 | Pulldown termination ZCTRL over-ride Enable: When this bit is set, it allows users to directly drive the termination bits of the impedance control using the data programmed in the ZQnOR.ZDATA field. Otherwise, the ZCTRL is generated automatically by the impedance control logic. |
| PU_ODT_ZDEN | 28 | rwNormal read/write | 0x0 | Pullup Termination ZCTRL over-ride Enable: When this bit is set, it allows users to directly drive the termination bits of the impedance control using the data programmed in the ZQnOR.ZDATA field. Otherwise, the ZCTRL is generated automatically by the impedance control logic. |
| ZSEGBYP | 27 | rwNormal read/write | 0x0 | Calibration segment bypass. When set bypass the current calibration segment during automatic calibration |
| ZLE_MODE | 26:25 | rwNormal read/write | 0x0 | VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB. The ZLE pin is responsible for latching the ZCTRL from the PUB ZQ onto the PVREF cell. 2b00 = Dynamic (PUB determines ZLE ON/OFF based on DFI/PHY update events. Recommended mode) 2b01 = ZLE always ON (ZCTRL codes may update to the PVREF cell in the midst of DRAM read/write traffic. Not recommended). 2b10 = ZLE always OFF (Turns off all ZCTRL updates to PVREF cell despite change in PVT conditions. Not recommended) 2b11 = Reserved |
| ODT_ADJUST | 24:22 | rwNormal read/write | 0x0 | Termination adjustment. Valid values are: 3b000 = No adjustment 3b001 = Adjust calibrated termination by 2/8 to obtain 1.25x of original strength 3b010 = Adjust calibrated termination by 3/8 to obtain 1.375x of original strength 3b011 = Adjust calibrated termination by 4/8 to obtain 1.5x of original strength 3b100 = Adjust calibrated termination by 3/4 to obtain 0.75x of original strength 3b011 = Adjust calibrated termination by 2/3 to obtain 0.625x of original strength 3b011 = Adjust calibrated termination by 1/2 to obtain 0.5x of original strength 3b111 = Reserved |
| PD_DRV_ADJUST | 21:19 | rwNormal read/write | 0x0 | Pulldown drive strength adjustment. Valid values are: 3b000 = No adjustment 3b001 = Adjust calibrated drive strength by 2/8 to obtain 1.25x of original strength 3b010 = Adjust calibrated drive strength by 3/8 to obtain 1.375x of original strength 3b011 = Adjust calibrated drive strength by 4/8 to obtain 1.5x of original strength 3b100 = Adjust calibrated drive strength by 3/4 to obtain 0.75x of original strength 3b011 = Adjust calibrated drive strength by 2/3 to obtain 0.625x of original strength 3b011 = Adjust calibrated drive strength by 1/2 to obtain 0.5x of original strength 3b111 = Reserved |
| PU_DRV_ADJUST | 18:16 | rwNormal read/write | 0x0 | Pullup drive strength adjustment. Valid values are: 3b000 = No adjustment 3b001 = Adjust calibrated drive strength by 2/8 to obtain 1.25x of original strength 3b010 = Adjust calibrated drive strength by 3/8 to obtain 1.375x of original strength 3b011 = Adjust calibrated drive strength by 4/8 to obtain 1.5x of original strength 3b100 = Adjust calibrated drive strength by 3/4 to obtain 0.75x of original strength 3b011 = Adjust calibrated drive strength by 2/3 to obtain 0.625x of original strength 3b011 = Adjust calibrated drive strength by 1/2 to obtain 0.5x of original strength 3b111 = Reserved |
| ZPROG_DRAM_ODT | 15:12 | rwNormal read/write | 0x7 | Impedance Divide Ratio: Selects the external resistor divide ratio to be used for host side pullup drive calibration in LPDDR4 mode. This field is used only for LPDDR4 calibration. |
| ZPROG_HOST_ODT | 11:8 | rwNormal read/write | 0x7 | Impedance Divide Ratio: Selects the external resistor divide ratio to be used for host-side termination calibration. For DDR3 calibration, this field controls both PU and PD termination For DDR4 calibration, this field controls PU termination For LPDDR4 calibration, this field controls PD termination |
| ZPROG_ASYM_DRV_PD | 7:4 | rwNormal read/write | 0xB | Impedance Divide Ratio: Select the external resistor divide ratio to be used for pulldown drive calibration during asymmetric drive strength calibration. If symmetric drive strength calibration is desired, program this register field to the same value as ZPROG_ASYM_PU_DRV. |
| ZPROG_ASYM_DRV_PU | 3:0 | rwNormal read/write | 0xB | Impedance Divide Ratio: Select the external resistor divide ratio to be used for pullup drive calibration during asymmetric drive strength calibration. If symmetric drive strength calibration is desired, program this register field to the same value as ZPROG_ASYM_DRV_PD. This field is unused for LPDDR4 calibration. |