ZQCR (DDR_PHY) Register Description
| Register Name | ZQCR |
|---|---|
| Offset Address | 0x0000000680 |
| Absolute Address | 0x00FD080680 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x008A2858 |
| Description | ZQ Impedance Control Register |
ZQCR (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:26 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| ZQREFISELRANGE | 25 | rwNormal read/write | 0x0 | ZQ Internal VREF generator REFSEL range select: selects the ZQ internal VREF generator's voltage range. |
| PGWAIT_FRQB | 24:19 | rwNormal read/write | 0x11 | Programmable Wait for frequency B: specifies the number of clock cycles to remain in the WAIT state of the Impedance Controller FSM Calculated as ceiling[40 ns/Frq B period] Default: DDR3-1600 |
| PGWAIT_FRQA | 18:13 | rwNormal read/write | 0x11 | Programmable Wait for frequency A: specifies the number of clock cycles to remain in the WAIT state of the Impedance Controller FSM Calculated as ceiling[40 ns/Frq A period] Default: DDR3-1600 |
| ZQREFPEN | 12 | rwNormal read/write | 0x0 | ZQ VREF Pad Enable: Enables the pass gate between (to connect) VREF and PAD. |
| ZQREFIEN | 11 | rwNormal read/write | 0x1 | ZQ Internal VREF Enable: Enables the generation of VREF for ZQ internal I/Os. |
| ODT_MODE | 10:9 | rwNormal read/write | 0x0 | Choice of termination mode. This field controls how ZQnPR0.ZPROG_HOST_ODT field is used 2b00 - DDR3 style symmetric termination calibration - ZQnPR0.ZPROG_HOST_ODT applies to both pull-up and pulldown termination 2b01 - DDR4/LPDDR3 style pull-up only termination calibration - ZQnPR0.ZPROG_HOST_ODT applies only to pull-up termination 2b10 - LPDDR4 style pulldown only termination calibration - ZQnPR0.ZPROG_HOST_ODT applies only to pulldown termination 2b11 - termination off calibration. ZQnPR0.ZPROG_HOST_ODT is ignored and ZCTRL[39:20] will be driven to 0x0 in PVREF cell |
| FORCE_ZCAL_VT_UPDATE | 8 | rwNormal read/write | 0x0 | When set to 1b1, forces a ZCAL VT update to the impedance calibration FSM. A write of 1b1 must be followed by a write of 1b0 to disable the request. This is a good alternative to the PHY and DFI update request signals. |
| IODLMT | 7:5 | rwNormal read/write | 0x2 | IO VT Drift Limit: Specifies the minimum change in the Impedance calibration VT code in one direction which should result in a DFI Control/PHY update request. The limit is specified in terms of binary ZCTRL values. A value of 1b0 disables the assertion of the IO VT drift status signal. |
| AVGEN | 4 | rwNormal read/write | 0x1 | Averaging algorithm enable, if set, enables averaging algorithm |
| AVGMAX | 3:2 | rwNormal read/write | 0x2 | Maximum number of averaging rounds to be used by averaging algorithm. Valid values are: 2b00 = 2 rounds 2b01 = 4 rounds 2b10 = 8 rounds 2b11 = 16 rounds |
| ZCALT | 1 | rwNormal read/write | 0x0 | 0' - calibration always ON in background. To stop calibration program PIR.ZCALBYP.'1' - calibration controlled by DFI/PHY update. ZCAL FSM runs calibration for all segments once after the update is received. Note: This register field should always be programmed with a value of 1'b0. Value of 1'b1 is not supported. |
| ZQPD | 0 | rwNormal read/write | 0x0 | ZQ Power Down; Powers down, if set, all PZQ cells |