ZQCS_CTRL0 (DDR_QOS_CTRL) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ZQCS_CTRL0 (DDR_QOS_CTRL) Register Description

Register NameZQCS_CTRL0
Offset Address0x0000000014
Absolute Address 0x00FD090014 (DDR_QOS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionZQCS Control Register 0

ZQCS_CTRL0 (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1razRead as zero0x0Reserved for future use
ENABLE 0rwNormal read/write0x0Enable ZQCS control through QoS Controller