ZQCS_CTRL1 (DDR_QOS_CTRL) Register Description
| Register Name | ZQCS_CTRL1 |
|---|---|
| Offset Address | 0x0000000018 |
| Absolute Address | 0x00FD090018 (DDR_QOS_CTRL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | ZQCS Control Register 2 |
ZQCS_CTRL1 (DDR_QOS_CTRL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | razRead as zero | 0x0 | Reserved for future use |
| VSYNC_CNT | 3:0 | rwNormal read/write | 0x0 | Software Programmable register to issue ZQCS to DDRC after programmable VSYNC pulse count |