ZQCS_STATUS (DDR_QOS_CTRL) Register Description
| Register Name | ZQCS_STATUS |
|---|---|
| Offset Address | 0x000000001C |
| Absolute Address | 0x00FD09001C (DDR_QOS_CTRL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | ZQCS Status Register |
ZQCS_STATUS (DDR_QOS_CTRL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | Reserved for future use |
| BUSY | 0 | roRead-only | 0x0 | QoS Controller may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the uMCTL2. It is recommended not to perform ZQCS operations when this signal is high. 0 - Indicates that the QoS Controller can initiate a ZQCS operation 1 - Indicates that ZQCS operation has not been initiated yet in the uMCTL2 |