ZQCTL0_SHADOW (DDRC) Register Description
| Register Name | ZQCTL0_SHADOW |
|---|---|
| Offset Address | 0x0000002180 |
| Absolute Address | 0x00FD072180 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x02000040 |
| Description | ZQ Control Shadow Register 0 |
All register fields are static, unless described otherwise in the register field description. Static registers can only be written when the controller is in reset.
ZQCTL0_SHADOW (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dis_auto_zq | 31 | rwNormal read/write | 0x0 | - 1 - Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. Programming Mode: Dynamic |
| dis_srx_zqcl | 30 | rwNormal read/write | 0x0 | - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh exit. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh exit. Programming Mode: Quasi-dynamic Group 2 and Group 4 |
| zq_resistor_shared | 29 | rwNormal read/write | 0x0 | - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 - ZQ resistor is not shared. |
| dis_mpsmx_zqcl | 28 | rwNormal read/write | 0x0 | - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. |
| t_zq_long_nop | 26:16 | rwNormal read/write | 0x200 | tZQoper for DDR3/DDR4, tZQCL for LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. LPDDR3: program this to tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. |
| t_zq_short_nop | 9:0 | rwNormal read/write | 0x40 | tZQCS for DDR3/DD4/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. Program this to tZQCS/2 and round it up to the next integer value. Unit: Clock cycles. |