ZQCTL1 (DDRC) Register Description
| Register Name | ZQCTL1 |
|---|---|
| Offset Address | 0x0000000184 |
| Absolute Address | 0x00FD070184 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x02000100 |
| Description | ZQ Control Register 1 |
This register is static. Static registers can only be written when the controller is in reset.
ZQCTL1 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| t_zq_reset_nop | 29:20 | rwNormal read/write | 0x20 | tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For LPDDR3/LPDDR4 designs, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. |
| t_zq_short_interval_x1024 | 19:0 | rwNormal read/write | 0x100 | Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. |