ZQCTL2 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ZQCTL2 (DDRC) Register Description

Register NameZQCTL2
Offset Address0x0000000188
Absolute Address 0x00FD070188 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionZQ Control Register 2

This register is dynamic. Dynamic registers can be written at any time during operation.

ZQCTL2 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
zq_reset 0rwNormal read/write0x0For LPDDR3/LPDDR4 designs, setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes.