ZQCTL2 (DDRC) Register Description
Register Name | ZQCTL2 |
Offset Address | 0x0000000188 |
Absolute Address |
0x00FD070188 (DDRC)
|
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | ZQ Control Register 2 |
This register is dynamic. Dynamic registers can be written at any time during operation.
ZQCTL2 (DDRC) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
zq_reset | 0 | rwNormal read/write | 0x0 | For LPDDR3/LPDDR4 designs, setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. |