afifm0M_intfpd_max_comb_ot (FPD_GPV) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

afifm0M_intfpd_max_comb_ot (FPD_GPV) Register Description

Register Nameafifm0M_intfpd_max_comb_ot
Offset Address0x0000045114
Absolute Address 0x00FD745114 (FPD_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMaximum number of combined outstanding transactions

A value of 0 for both the integer and fractional parts disables the programmable regulation so that the configuration limits apply. A value of 0 for the fractional part programs disables the regulation of fractional outstanding transactions. The regulation of the combined outstanding transaction limit also requires that you set the en_awar_ot control bit of the QoS control register.

afifm0M_intfpd_max_comb_ot (FPD_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
awar_max_oti14:8rwNormal read/write0x0Integer part of max combined outstanding AW/AR addresses.
awar_max_otf 7:0rwNormal read/write0x0Fraction part of max combined outstanding AW/AR addresses.