auto_flushed_pkts (GEM) Register Description
| Register Name | auto_flushed_pkts |
|---|---|
| Offset Address | 0x00000001B4 |
| Absolute Address |
0x00FF0B01B4 (GEM0) 0x00FF0C01B4 (GEM1) 0x00FF0D01B4 (GEM2) 0x00FF0E01B4 (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Receive DMA Flushed Packets |
auto_flushed_pkts (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:16 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| count | 15:0 | rwNormal read/write | 0x0 | Flushed RX pkts counter. A 16 bit register counting the number of frames that have been flushed from the receive SRAM based packet buffer due to one of the following reasons..1.When partial store and forward mode is enabled or bit 24 of the DMA configuration register is enabled, a packet is received while there is no AMBA (AHB/AXI) resource. 2.When partial store and forward mode is enabled and an AMBA (AHB/AXI) error is encountered while writing the packet data to external memory. When bit 18 of the network control register(software action to flush a packet from the head of the PBUF queue) is pulsed and the GEM DMA is not currently busy. |