axi_max_pipeline (GEM) Register Description
| Register Name | axi_max_pipeline |
|---|---|
| Offset Address | 0x0000000054 |
| Absolute Address |
0x00FF0B0054 (GEM0) 0x00FF0C0054 (GEM1) 0x00FF0D0054 (GEM2) 0x00FF0E0054 (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000101 |
| Description | Used to set the maximum amnount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO. Note: We recommend to use the default setting for this register. |
axi_max_pipeline (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:16 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| aw2w_max_pipeline | 15:8 | rwNormal read/write | 0x1 | Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the AW channel. |
| ar2r_max_pipeline | 7:0 | rwNormal read/write | 0x1 | Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel. |