csu_isr (CSU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

csu_isr (CSU) Register Description

Register Namecsu_isr
Offset Address0x0000000020
Absolute Address 0x00FFCA0020 (CSU)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionCSU Interrupt Status

csu_isr (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CSU_PL_ISO15wtcReadable, write a 1 to clear0x0Indicates that the CSU has enabled the isolation for the PS / PL. Communication between the PS and PL has been disabled.
CSU_RAM_ECC_ERROR14wtcReadable, write a 1 to clear0x0Uncorrectable ECC error encountered on CSU RAM. CSU Secure Processor will automatically reset to clear the error.
tamper13wtcReadable, write a 1 to clear0x0Tamper response interrupt. See tamper response Status register to see which tamper occurred.
apb_slverr11wtcReadable, write a 1 to clear0x0APB slave error
tmr_fatal10wtcReadable, write a 1 to clear0x0CSU SPB has encountered a fatal error in the triple-redundant implementation and will reset
pl_seu_error 9wtcReadable, write a 1 to clear0x0PL SEU error, the feature must be enabled in the PL bitstream.
aes_error 8wtcReadable, write a 1 to clear0x0AES decryption error
pcap_wr_overflow 7wtcReadable, write a 1 to clear0x0PCAP write FIFO overflow
pcap_rd_overflow 6wtcReadable, write a 1 to clear0x0PCAP read FIFO overflow
pl_por_b 5wtcReadable, write a 1 to clear0x0Indicates the PL is powered up
pl_init 4wtcReadable, write a 1 to clear0x0PL initialization complete
pl_done 3wtcReadable, write a 1 to clear0x0PL done
sha_done 2wtcReadable, write a 1 to clear0x0SHA done
rsa_done 1wtcReadable, write a 1 to clear0x0RSA done
aes_done 0wtcReadable, write a 1 to clear0x0AES done