ctrl (FPD_SLCR_SECURE) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ctrl (FPD_SLCR_SECURE) Register Description

Register Namectrl
Offset Address0x0000000004
Absolute Address 0x00FD690004 (FPD_SLCR_SECURE)
Width 1
TyperwNormal read/write
Reset Value0x00000000
DescriptionGeneral control register for the LPD SLCR SECURE.

ctrl (FPD_SLCR_SECURE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
slverr_enable 0rwNormal read/write0x0By default, invalid address requests are ignored. However, a maskable interrupt exists. By enabling this slverr_enable, invalid address requests cause a slverr to occur. Enable/Disable SLVERR during address decode failure.
0: SLVERR is disabled. Register write is ignored. Read returns 0.
1: SLVERR is enabled. SLVERR is asserted. Register write is ignored. Read returns 0.