designcfg_debug10 (GEM) Register Description
| Register Name | designcfg_debug10 |
|---|---|
| Offset Address | 0x00000002A4 |
| Absolute Address |
0x00FF0B02A4 (GEM0) 0x00FF0C02A4 (GEM1) 0x00FF0D02A4 (GEM2) 0x00FF0E02A4 (GEM3) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x22242222 |
| Description | Design Configuration Register 10 |
designcfg_debug10 (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| emac_bus_width | 31:28 | roRead-only | 0x2 | Takes the value of the `gem_emac_bus_width DEFINE. 1 - The MAC has a datawidth of 32bits. 2 - The MAC has a datawidth of 64bits. 4 - The MAC has a datawidth of 128bits |
| tx_pbuf_data | 27:24 | roRead-only | 0x2 | Takes the value of the `gem_tx_pbuf_data DEFINE. 1 - The TX DPRAM has a datawidth of 32bits. 2 - The TX DPRAM has a datawidth of 64bits. 4 - The TX DPRAM has a datawidth of 128bits |
| rx_pbuf_data | 23:20 | roRead-only | 0x2 | Takes the value of the `gem_rx_pbuf_data DEFINE. 1 - The RX DPRAM has a datawidth of 32bits. 2 - The RX DPRAM has a datawidth of 64bits. 4 - RX The DPRAM has a datawidth of 128bits |
| axi_access_pipeline_bits | 19:16 | roRead-only | 0x4 | Takes the value of the `gem_axi_access_pipeline_bits DEFINE |
| axi_tx_descr_rd_buff_bits | 15:12 | roRead-only | 0x2 | Takes the value of the `gem_axi_tx_descr_rd_buff_bits DEFINE |
| axi_rx_descr_rd_buff_bits | 11:8 | roRead-only | 0x2 | Takes the value of the `gem_axi_rx_descr_rd_buff_bits DEFINE |
| axi_tx_descr_wr_buff_bits | 7:4 | roRead-only | 0x2 | Takes the value of the `gem_axi_tx_descr_wr_buff_bits DEFINE |
| axi_rx_descr_wr_buff_bits | 3:0 | roRead-only | 0x2 | Takes the value of the `gem_axi_rx_descr_wr_buff_bits DEFINE |