designcfg_debug5 (GEM) Register Description
| Register Name | designcfg_debug5 |
|---|---|
| Offset Address | 0x0000000290 |
| Absolute Address |
0x00FF0B0290 (GEM0) 0x00FF0C0290 (GEM1) 0x00FF0D0290 (GEM2) 0x00FF0E0290 (GEM3) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x502F2744 |
| Description | Design Configuration Register 5 |
designcfg_debug5 (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| axi_prot_value | 31:29 | roRead-only | 0x2 | Takes the value of the `gem_axi_prot_value DEFINE |
| tsu_clk | 28 | roRead-only | 0x1 | Takes the value of the `gem_tsu_clk DEFINE |
| rx_buffer_length_def | 27:20 | roRead-only | 0x2 | Takes the value of the `gem_rx_buffer_length_def DEFINE |
| tx_pbuf_size_def | 19 | roRead-only | 0x1 | Takes the value of the `gem_tx_pbuf_size_def DEFINE |
| rx_pbuf_size_def | 18:17 | roRead-only | 0x3 | Takes the value of the `gem_rx_pbuf_size_def DEFINE |
| endian_swap_def | 16:15 | roRead-only | 0x2 | Takes the value of the `gem_endian_swap_def DEFINE |
| mdc_clock_div | 14:12 | roRead-only | 0x2 | Takes the value of the `gem_mdc_clock_div DEFINE |
| dma_bus_width_def | 11:10 | roRead-only | 0x1 | Takes the value of the `gem_dma_bus_width_def DEFINE |
| phy_ident | 9 | roRead-only | 0x1 | Takes the value of the `gem_phy_ident DEFINE |
| tsu | 8 | roRead-only | 0x1 | Takes the value of the `gem_tsu DEFINE |
| tx_fifo_cnt_width | 7:4 | roRead-only | 0x4 | Takes the value of the `gem_tx_fifo_cnt_width DEFINE |
| rx_fifo_cnt_width | 3:0 | roRead-only | 0x4 | Takes the value of the `gem_rx_fifo_cnt_width DEFINE |