dma_config (GEM) Register Description
| Register Name | dma_config |
|---|---|
| Offset Address | 0x0000000010 |
| Absolute Address |
0x00FF0B0010 (GEM0) 0x00FF0C0010 (GEM1) 0x00FF0D0010 (GEM2) 0x00FF0E0010 (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00020784 |
| Description | DMA Configuration Register |
dma_config (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| dma_addr_bus_width_1 | 30 | rwNormal read/write | 0x0 | DMA address bus width. 0 = 32b, 1 = 64b. |
| tx_bd_extended_mode_en | 29 | rwNormal read/write | 0x0 | Enable TX extended BD mode. See TX BD control register definition for description of feature. |
| rx_bd_extended_mode_en | 28 | rwNormal read/write | 0x0 | Enable RX extended BD mode. See RX BD control register definition for description of feature. |
| Reserved | 27 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| force_max_amba_burst_tx | 26 | rwNormal read/write | 0x0 | Force max length bursts on TX. Force the TX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer) transfers as defined by bits 4:0 of this register, even when there is less that max burst data bytes to read. Residual data read is ignored. Does not apply on bursts that break 1k boundary rule. |
| force_max_amba_burst_rx | 25 | rwNormal read/write | 0x0 | Force max length bursts on RX. Force the RX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer)transfers, even if there is less than max burst real packet data required to write. Any extra bytes of pad data is set to 0x00. Does not apply on bursts that break 1k boundary rule. |
| force_discard_on_err | 24 | rwNormal read/write | 0x0 | Auto Discard RX pkts during lack of resource. When set, the GEM DMA will automatically discard receive packets from the receiver packet buffer memory when no AMBA (AHB/AXI) resource is available. When low, then received packets will remain to be stored in the SRAM based packet buffer until AMBA (AHB/AXI) buffer resource next becomes available. A write to this bit is ignored if the DMA is not configured in the packet buffer full store and forward mode. |
| rx_buf_size | 23:16 | rwNormal read/write | 0x2 | DMA receive buffer size in external AMBA (AHB/AXI) system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes.0x01 corresponds to buffers of 64 bytes0x02 corresponds to 128 bytes etc.For example:0x02: 128 byte.0x18: 1536 byte (1*max length frame/buffer)0xA0: 10240 byte (1*10K jumbo frame/buffer)Note that this value should never be written as zero.Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. |
| Reserved | 15:12 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| tx_pbuf_tcp_en | 11 | rwNormal read/write | 0x0 | Transmitter IP, TCP and UDP checksum generation offload enable (not supported when in TX Partial Store and Forward mode). When set, the transmitter checksum generation engine is enabled, to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected. If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as zero, ignored on write. |
| tx_pbuf_size | 10 | rwNormal read/write | 0x1 | Transmitter packet buffer memory size. 0: Do not use top address bit (16 KB) 1: Use full configured addressable space (32KB) Note: This field is used for the DMA packet buffer. Note:The reset value of this field is equal to the gem_tx_pbuf_size_def define, which is user configurable. Note: Setting this bit to 1b0 halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GEM. It is important to set this bit to 1b1 if the full configured physical memory is available. The value in brackets above represents the size that would result for the default maximum configured memory size of 32 Kbytes. |
| rx_pbuf_size | 9:8 | rwNormal read/write | 0x3 | Rx packet buffer memory size: 00: Do not use top three address bits (4 KB) 01: Do not use top two address bits (8 KB) 10: Do not use top address bit (16 KB) 11: Use full configured addressable space (32 KB) Note: This field is used for the DMA packet buffer. Note: A setting other than 2b11 reduces the amount of memory used for the receive packet buffer. This reduces the amount of system memory used by the GEM. Note: The reset value is equal to the gem_rx_pbuf_size_def define, which is user configurable. It is important to set these bits to 2b11 if the full configured physical memory is available. The value in brackets above represents the size that would result for the default maximum configured memory size of 32KB. |
| endian_swap_packet | 7 | rwNormal read/write | 0x1 | endian swap mode enable for packet data accesses. When set, selects swapped endianism for AMBA (AHB/AXI) transfers. When clear, selects little endian mode. |
| endian_swap_management | 6 | rwNormal read/write | 0x0 | endian swap mode enable for management descriptor accesses. When set, selects swapped endianism for AMBA (AHB/AXI) transfers. When clear, selects little endian mode. |
| Reserved | 5 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| amba_burst_length | 4:0 | rwNormal read/write | 0x4 | Selects the burst length to attempt to use on the AMBA (AHB/AXI) when transferring frame data. Not used for DMA management operations and only used where space and data size allow and respecting AXI/AHB burst boundary rules. One-hot priority encoding enforced automatically on register writes as follows, where x represents dont care: 1xxxx: Attempt to use bursts of up to 16. 01xxx: Attempt to use bursts of up to 8. 001xx: Attempt to use bursts of up to 4. 0001x: Always use SINGLE bursts. 00001: Always use SINGLE bursts. 00000: Reserved |