efuse_isr (EFUSE) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

efuse_isr (EFUSE) Register Description

Register Nameefuse_isr
Offset Address0x0000000030
Absolute Address 0x00FFCC0030 (EFUSE)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptioneFuse Interrupt Status

efuse_isr (EFUSE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
APB_SLVERR31wtcReadable, write a 1 to clear0x0APB slave error
Reserved30:5razRead as zero0x0reserved
CACHE_ERROR 4wtcReadable, write a 1 to clear0x0Indicates that there was a parity error in the EFUSE cache.
RD_ERROR 3wtcReadable, write a 1 to clear0x0Indicatest that a RD was requested to a restricted FUSE. RD operation aborted.
RD_DONE 2wtcReadable, write a 1 to clear0x0Indicates that the RD operation has completed. RD data is now available in the EFUSE_RD_DATA register.
PGM_ERROR 1wtcReadable, write a 1 to clear0x0Inidcates that PGM was requested to a restricted FUSE. PGM operation was aborted.
PGM_DONE 0wtcReadable, write a 1 to clear0x0Indicates that the PGM operation has completed