err_ctrl (XMPU_SINK) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

err_ctrl (XMPU_SINK) Register Description

Register Nameerr_ctrl
Offset Address0x000000FFEC
Absolute Address 0x00FD4FFFEC (FPD_XMPU_SINK)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionError Signal Control. APB slave error signal.

err_ctrl (XMPU_SINK) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
pslverr 0rwNormal read/write0x0Enable the PSLVERR signal back to APB interconnect when an access violation occurs.
0: disable error signal.
1: assert error signal for access violations.
Note: The [addr_decode_err] interrupt bit is set in the ISR regardless of the setting of this bit.