gdma_cfg (FPD_SLCR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

gdma_cfg (FPD_SLCR) Register Description

Register Namegdma_cfg
Offset Address0x0000003000
Absolute Address 0x00FD613000 (FPD_SLCR)
Width 7
TyperoRead-only
Reset Value0x00000048
DescriptionGDMA RF2 Configuation

gdma_cfg (FPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
BUS_WIDTH 6:5roRead-only0x2Indicates the AXI Bus Width
00 = 32 bit
01 = 64 bit
10 = 128 bit
11 = 256 bit
NUM_CH 4:0roRead-only0x8Indicates Number of implemneted channels