imr (XMPU_SINK) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

imr (XMPU_SINK) Register Description

Register Nameimr
Offset Address0x000000FF14
Absolute Address 0x00FD4FFF14 (FPD_XMPU_SINK)
Width 1
TyperoRead-only
Reset Value0x00000001
DescriptionInterrupt Mask.

imr (XMPU_SINK) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err 0roRead-only0x1Access violation (poisoned AXI transaction or register access error).
Read-only.
0: enabled.
1: masked (disabled).
If the ISR bit = 1 (asserted interrupt) and the IMR bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Software checks the ISR to determine the cause of the interrupt.