imr (XMPU_SINK) Register Description
Register Name | imr |
---|---|
Offset Address | 0x000000FF14 |
Absolute Address | 0x00FD4FFF14 (FPD_XMPU_SINK) |
Width | 1 |
Type | roRead-only |
Reset Value | 0x00000001 |
Description | Interrupt Mask. |
imr (XMPU_SINK) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
addr_decode_err | 0 | roRead-only | 0x1 | Access violation (poisoned AXI transaction or register access error). Read-only. 0: enabled. 1: masked (disabled). If the ISR bit = 1 (asserted interrupt) and the IMR bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Software checks the ISR to determine the cause of the interrupt. |