int_mask (GEM) Register Description
| Register Name | int_mask |
|---|---|
| Offset Address | 0x0000000030 |
| Absolute Address |
0x00FF0B0030 (GEM0) 0x00FF0C0030 (GEM1) 0x00FF0D0030 (GEM2) 0x00FF0E0030 (GEM3) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x3FFFFFFF |
| Description | The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register. |
int_mask (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| Reserved | 30 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| tsu_timer_comparison_mask | 29 | roRead-only | 0x1 | Enable TSU timer comparison interrupt mask. |
| wol_event_received_mask | 28 | roRead-only | 0x1 | A read of this register returns the value of the WOL event received mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| rx_lpi_indication_mask | 27 | roRead-only | 0x1 | A read of this register returns the value of the RX LPI indication mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written |
| tsu_seconds_register_increment_mask | 26 | roRead-only | 0x1 | A read of this register returns the value of the TSU seconds register increment mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| ptp_pdelay_resp_frame_transmitted_mask | 25 | roRead-only | 0x1 | A read of this register returns the value of the PTP pdelay_resp frame transmitted mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| ptp_pdelay_req_frame_transmitted_mask | 24 | roRead-only | 0x1 | A read of this register returns the value of the PTP pdelay_req frame transmitted mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| ptp_pdelay_resp_frame_received_mask | 23 | roRead-only | 0x1 | A read of this register returns the value of the PTP pdelay_resp frame received mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| ptp_pdelay_req_frame_received_mask | 22 | roRead-only | 0x1 | A read of this register returns the value of the PTP pdelay_req frame received mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| ptp_sync_frame_transmitted_mask | 21 | roRead-only | 0x1 | A read of this register returns the value of the PTP sync frame transmitted mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| ptp_delay_req_frame_transmitted_mask | 20 | roRead-only | 0x1 | A read of this register returns the value of the PTP delay_req frame transmitted mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| ptp_sync_frame_received_mask | 19 | roRead-only | 0x1 | A read of this register returns the value of the PTP sync frame received mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| ptp_delay_req_frame_received_mask | 18 | roRead-only | 0x1 | A read of this register returns the value of the PTP delay_req frame received mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| pcs_link_partner_page_mask | 17 | roRead-only | 0x1 | A read of this register returns the value of the PCS link partner page mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| pcs_auto_negotiation_complete_interrupt_mask | 16 | roRead-only | 0x1 | A read of this register returns the value of the PCS auto-negotiation complete interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| external_interrupt_mask | 15 | roRead-only | 0x1 | external interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| pause_frame_transmitted_interrupt_mask | 14 | roRead-only | 0x1 | pause frame transmitted interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| pause_time_zero_interrupt_mask | 13 | roRead-only | 0x1 | pause time zero interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| pause_frame_with_non_zero_pause_quantum_interrupt_mask | 12 | roRead-only | 0x1 | pause frame with non-zero pause quantum interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| resp_not_ok_interrupt_mask | 11 | roRead-only | 0x1 | bresp/hresp not OK interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| receive_overrun_interrupt_mask | 10 | roRead-only | 0x1 | receive overrun interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| link_change_interrupt_mask | 9 | roRead-only | 0x1 | A read of this register returns the value of the link change interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| not_used | 8 | roRead-only | 0x1 | Not used |
| transmit_complete_interrupt_mask | 7 | roRead-only | 0x1 | transmit complete interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| amba_error_interrupt_mask | 6 | roRead-only | 0x1 | transmit frame corruption due to AMBA (AHB/AXI) error interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| retry_limit_exceeded_or_late_collision | 5 | roRead-only | 0x1 | A read of this register returns the value of the retry limit exceeded or late collision (gigabit mode only) interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| transmit_buffer_under_run_interrupt_mask | 4 | roRead-only | 0x1 | transmit buffer under run interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| transmit_used_bit_read_interrupt_mask | 3 | roRead-only | 0x1 | transmit used bit read interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| receive_used_bit_read_interrupt_mask | 2 | roRead-only | 0x1 | receive used bit read interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| receive_complete_interrupt_mask | 1 | roRead-only | 0x1 | receive complete interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| management_done_interrupt_mask | 0 | roRead-only | 0x1 | management done interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |