int_status (GEM) Register Description
| Register Name | int_status |
|---|---|
| Offset Address | 0x0000000024 |
| Absolute Address |
0x00FF0B0024 (GEM0) 0x00FF0C0024 (GEM1) 0x00FF0D0024 (GEM2) 0x00FF0E0024 (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Status - non-priority queing. |
This register indicates the source of an interrupt when the controller is not configured for priority queueing. The corresponding bit in the mask register must be clear for a bit in this register to be set. If any status bit is set, then the ethernet_int signal will be asserted. This register is write-to-clear (the gem_irq_read_clear IP define is set = 0).
int_status (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31 | roRead-only | 0x0 | reserved |
| Reserved | 30 | roRead-only | 0x0 | reserved |
| tsu_timer_comparison_interrupt | 29 | rwNormal read/write | 0x0 | TSU timer comparison interrupt. Indicates when TSU timer count value is equal to programmed value. |
| wol_interrupt | 28 | rwNormal read/write | 0x0 | WOL interrupt. Indicates a WOL event has been received. |
| receive_lpi_indication_status_bit_change | 27 | rwNormal read/write | 0x0 | Receive LPI indication status bit change |
| tsu_seconds_register_increment | 26 | rwNormal read/write | 0x0 | TSU seconds register increment indicates the register has incremented. |
| ptp_pdelay_resp_frame_transmitted | 25 | rwNormal read/write | 0x0 | PTP pdelay_resp frame transmitted indicates a PTP pdelay_resp frame has been transmitted. |
| ptp_pdelay_req_frame_transmitted | 24 | rwNormal read/write | 0x0 | PTP pdelay_req frame transmitted indicates a PTP pdelay_req frame has been transmitted. |
| ptp_pdelay_resp_frame_received | 23 | rwNormal read/write | 0x0 | PTP pdelay_resp frame received indicates a PTP pdelay_resp frame has been received. |
| ptp_pdelay_req_frame_received | 22 | rwNormal read/write | 0x0 | PTP pdelay_req frame received indicates a PTP pdelay_req frame has been received. |
| ptp_sync_frame_transmitted | 21 | rwNormal read/write | 0x0 | PTP sync frame transmitted indicates a PTP sync frame has been transmitted. |
| ptp_delay_req_frame_transmitted | 20 | rwNormal read/write | 0x0 | PTP delay_req frame transmitted indicates a PTP delay_req frame has been transmitted. |
| ptp_sync_frame_received | 19 | rwNormal read/write | 0x0 | PTP sync frame received indicates a PTP sync frame has been received. |
| ptp_delay_req_frame_received | 18 | rwNormal read/write | 0x0 | PTP delay_req frame received indicates a PTP delay_req frame has been received. |
| pcs_link_partner_page_received | 17 | rwNormal read/write | 0x0 | PCS link partner page received - set when a new base page or next page is received from the link partner. The first time this interrupt is received, it will indicate base page received and subsequent reads will indicate next pages. The next page and base page registers should only be read when this interrupt is signalled. For next pages, the link partner next page register should be read first to avoid the register being over written. This interrupt also indicates when the host should write a new page into the next page register. If further next page exchange is only required by the link partner, this register should be written with a null message page (0x2001). |
| pcs_auto_negotiation_complete | 16 | rwNormal read/write | 0x0 | PCS auto-negotiation complete - set once the internal PCS layer has completed auto-negotiation. |
| external_interrupt | 15 | rwNormal read/write | 0x0 | External interrupt - set when a rising edge has been detected on the ext_interrupt_in input pin. |
| pause_frame_transmitted | 14 | rwNormal read/write | 0x0 | Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin. |
| pause_time_elapsed | 13 | rwNormal read/write | 0x0 | Pause Time elapsed. set when either the pause time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field. |
| pause_frame_with_non_zero_pause_quantum_received | 12 | rwNormal read/write | 0x0 | Pause frame with non-zero pause quantum received - indicates a valid pause has been received that has a non-zero pause quantum field. |
| resp_not_ok | 11 | rwNormal read/write | 0x0 | bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. |
| receive_overrun | 10 | rwNormal read/write | 0x0 | Receive overrun - set when the receive overrun status bit gets set. |
| link_change | 9 | rwNormal read/write | 0x0 | Link change - set when the state of the link detected by the internal PCS changes state. |
| Reserved | 8 | roRead-only | 0x0 | reserved |
| transmit_complete | 7 | rwNormal read/write | 0x0 | Transmit complete - set when a frame has been transmitted. |
| amba_error | 6 | rwNormal read/write | 0x0 | Transmit frame corruption due to AMBA (AHB/AXI) error. Set if an error occurs whilst midway through reading transmit frame from external system memory, including HRESP errors(AHB), RRESP or BRESP(AXI) errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. |
| retry_limit_exceeded_or_late_collision | 5 | rwNormal read/write | 0x0 | Retry limit exceeded or late collision - transmit error. Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted). |
| transmit_under_run | 4 | rwNormal read/write | 0x0 | Transmit under run - this interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable. Note: If an under run occurs, the transmitter will force bad CRC and tx_er high. This interrupt is set if a transmitter status write back has not completed when another status write back is attempted. Note: When using the DMA interface configured for internal FIFO mode, this interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB/AXI error response was returned by the connected slave, or because a used bit was read. Note: When using the DMA interface configured for packet buffer mode, this bit will never be set. Note: When using the external FIFO interface, this interrupt is also set when the tx_r_underflow input was asserted during a frame transfer. |
| tx_used_bit_read | 3 | rwNormal read/write | 0x0 | TX used bit read - set when a transmit buffer descriptor is read with its used bit set. |
| rx_used_bit_read | 2 | rwNormal read/write | 0x0 | RX used bit read - set when a receive buffer descriptor is read with its used bit set. |
| receive_complete | 1 | rwNormal read/write | 0x0 | Receive complete - a frame has been stored in memory. |
| management_frame_sent | 0 | rwNormal read/write | 0x0 | Management frame sent - the PHY maintenance register has completed its operation. |