intfpdcci_intfpdmain_ib_ar_p (FPD_GPV) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

intfpdcci_intfpdmain_ib_ar_p (FPD_GPV) Register Description

Register Nameintfpdcci_intfpdmain_ib_ar_p
Offset Address0x0000042124
Absolute Address 0x00FD742124 (FPD_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAR channel peak rate

intfpdcci_intfpdmain_ib_ar_p (FPD_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ar_p31:24rwNormal read/write0x0channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.