isr (XMPU_SINK) Register Description
| Register Name | isr |
|---|---|
| Offset Address | 0x000000FF10 |
| Absolute Address | 0x00FD4FFF10 (FPD_XMPU_SINK) |
| Width | 1 |
| Type | wtcReadable, write a 1 to clear |
| Reset Value | 0x00000000 |
| Description | Interrupt Status and Clear. |
isr (XMPU_SINK) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| addr_decode_err | 0 | wtcReadable, write a 1 to clear | 0x0 | Access violation (poisoned AXI transaction or register access error). READ: 0: no interrupt. 1: interrupt asserted. WRITE: 0: no effect. 1: clear bit to 0. If a Status bit is 1 and its Mask is 0, then the interrupt signal is active to the interrupt controllers. The ERR_CTRL [PSLVERR] can enable a violation event to cause the XMPU_Sink to assert the PSLVERR signal back to the APB interconnect. |