itr (FPD_SLCR_SECURE) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

itr (FPD_SLCR_SECURE) Register Description

Register Nameitr
Offset Address0x0000000018
Absolute Address 0x00FD690018 (FPD_SLCR_SECURE)
Width 1
TypewoWrite-only
Reset Value0x00000000
DescriptionInterrupt Trigger

Write a 1 to set the interrupt status register related to this interrupt.

itr (FPD_SLCR_SECURE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err 0woWrite-only0x0Trigger an address decode error interrupt.
Writes:
0: ignored.
1: ISR register bit set to 1.