late_collisions (GEM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

late_collisions (GEM) Register Description

Register Namelate_collisions
Offset Address0x0000000144
Absolute Address 0x00FF0B0144 (GEM0)
0x00FF0C0144 (GEM1)
0x00FF0D0144 (GEM2)
0x00FF0E0144 (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionLate Collisions

late_collisions (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:10roRead-only0x0Reserved, read as 0, ignored on write.
count 9:0rwNormal read/write0x0Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e. both as a collision and a late collision. In gigabit mode, a late collision causes the transmission to be aborted, thus the single and multi collision registers are not updated.