multiple_collisions (GEM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

multiple_collisions (GEM) Register Description

Register Namemultiple_collisions
Offset Address0x000000013C
Absolute Address 0x00FF0B013C (GEM0)
0x00FF0C013C (GEM1)
0x00FF0D013C (GEM2)
0x00FF0E013C (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionMultiple Collision Frames

multiple_collisions (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:18roRead-only0x0Reserved, read as 0, ignored on write.
count17:0rwNormal read/write0x0Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no under run and not too many retries.