multiple_collisions (GEM) Register Description
Register Name | multiple_collisions |
---|---|
Offset Address | 0x000000013C |
Absolute Address |
0x00FF0B013C (GEM0) 0x00FF0C013C (GEM1) 0x00FF0D013C (GEM2) 0x00FF0E013C (GEM3) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Multiple Collision Frames |
multiple_collisions (GEM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:18 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
count | 17:0 | rwNormal read/write | 0x0 | Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no under run and not too many retries. |