network_config (GEM) Register Description
| Register Name | network_config |
|---|---|
| Offset Address | 0x0000000004 |
| Absolute Address |
0x00FF0B0004 (GEM0) 0x00FF0C0004 (GEM1) 0x00FF0D0004 (GEM2) 0x00FF0E0004 (GEM3) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00280000 |
| Description | The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC. |
network_config (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| uni_direction_enable | 31 | rwNormal read/write | 0x0 | Uni-direction-enable. When low the PCS will transmit idle symbols if the link goes down. When high the PCS can transmit frame data when the link is down. |
| ignore_ipg_rx_er | 30 | rwNormal read/write | 0x0 | Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode. |
| nsp_change | 29 | rwNormal read/write | 0x0 | Receive bad preamble. When set frames with non-standard preamble are not rejected. |
| ipg_stretch_enable | 28 | rwNormal read/write | 0x0 | IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register. |
| sgmii_mode_enable | 27 | rwNormal read/write | 0x0 | SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms. |
| ignore_rx_fcs | 26 | rwNormal read/write | 0x0 | Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frames DMA descriptor. For normal operation this bit must be set to zero. |
| en_half_duplex_rx | 25 | rwNormal read/write | 0x0 | Enable frames to be received in half-duplex mode while transmitting. |
| receive_checksum_offload_enable | 24 | rwNormal read/write | 0x0 | Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded. |
| disable_copy_of_pause_frames | 23 | rwNormal read/write | 0x0 | Disable copy of pause frames - set to one to prevent valid pause frames being copied to memory. When set, pause frames are not copied to memory regardless of the state of the copy all frames bit; whether a hash match is found or whether a type ID match is identified. If a destination address match is found the pause frame will be copied to memory. Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required. |
| data_bus_width | 22:21 | rwNormal read/write | 0x1 | Data bus width - set according to AMBA AXI or external FIFO data bus width. 00: 32 bit data bus width (External FIFO mode) 01: 64 bit AMBA AXI data bus width (AMBA AXI DMA mode) 10: Reserved 11: Reserved |
| mdc_clock_division | 20:18 | rwNormal read/write | 0x2 | MDC clock division - set according to cpu_1xclk speed. These three bits determine the number cpu_1xclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). 000: divide cpu_1xclk by 8 (cpu_1xclk up to 20 MHz) 001: divide cpu_1xclk by 16 (cpu_1xclk up to 40 MHz) 010: divide cpu_1xclk by 32 (cpu_1xclk up to 80 MHz) 011: divide cpu_1xclk by 48 (cpu_1xclk up to 120MHz) 100: divide cpu_1xclk by 64 (cpu_1xclk up to 160 MHz) 101: divide cpu_1xclk by 96 (cpu_1xclk up to 240 MHz) 110: divide cpu_1xclk by 128 (cpu_1xclk up to 320 MHz) 111: divide cpu_1xclk by 224 (cpu_1xclk up to 540 MHz) |
| fcs_remove | 17 | rwNormal read/write | 0x0 | FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode. |
| length_field_error_frame_discard | 16 | rwNormal read/write | 0x0 | Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600. |
| receive_buffer_offset | 15:14 | rwNormal read/write | 0x0 | Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer. |
| pause_enable | 13 | rwNormal read/write | 0x0 | Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated. |
| retry_test | 12 | rwNormal read/write | 0x0 | Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle. |
| pcs_select | 11 | rwNormal read/write | 0x0 | PCS select - selects between MII/GMII and TBI. Must be set for SGMII operation.0: GMII/MII interface enabled, TBI disabled1: TBI enabled, GMII/MII disabled |
| gigabit_mode_enable | 10 | rwNormal read/write | 0x0 | Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation.0: 10/100 operation using MII or TBI interface1: Gigabit operation using GMII or TBI interface |
| external_address_match_enable | 9 | rwNormal read/write | 0x0 | External address match enable - when set the external address match interface can be used to copy frames to memory. |
| receive_1536_byte_frames | 8 | rwNormal read/write | 0x0 | Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes. |
| unicast_hash_enable | 7 | rwNormal read/write | 0x0 | Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. |
| multicast_hash_enable | 6 | rwNormal read/write | 0x0 | Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. |
| no_broadcast | 5 | rwNormal read/write | 0x0 | No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted. |
| copy_all_frames | 4 | rwNormal read/write | 0x0 | Copy all frames - when set to logic one, all valid frames will be accepted. |
| jumbo_frames | 3 | rwNormal read/write | 0x0 | Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10,240 bytes. |
| discard_non_vlan_frames | 2 | rwNormal read/write | 0x0 | Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic. |
| full_duplex | 1 | rwNormal read/write | 0x0 | Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin. |
| speed | 0 | rwNormal read/write | 0x0 | Speed select: 0: 10 Mb/s 1: 100 Mb/s Note: The value of this bit is reflected on the speed_mode[0] output pin. Note: 10 and 100 Mb/s are supported in RGMII only (not in SGMII). |