network_control (GEM) Register Description
| Register Name | network_control |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address |
0x00FF0B0000 (GEM0) 0x00FF0C0000 (GEM1) 0x00FF0D0000 (GEM2) 0x00FF0E0000 (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | The network control register contains general MAC control functions for both receiver and transmitter. |
network_control (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:26 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| Reserved | 25 | rwNormal read/write | 0x0 | Reserved. Writeable register. Ignore on read. |
| one_step_sync_mode | 24 | rwNormal read/write | 0x0 | 1588 One Step Sync Mode. Write 1 to enable. Replace timestamp field in the 1588 header for TX Sync Frames with current TSU timer value. |
| ext_tsu_port_enable | 23 | rwNormal read/write | 0x0 | External TSU timer port enable (1 = enable) Note: This bit is only valid for GEM 0. |
| store_udp_offset | 22 | rwNormal read/write | 0x0 | Store UDP / TCP offset to memory. Setting this bit to one will cause the upper 16-bits of the CRC of every received frame to be replaced with the offset from start of frame to the beginning of the UDP or TCP header. The lower 16-bits of the CRC are replaced with zero and reserved for future use. The offset is measured in units of 2 bytes. Set to zero for normal operation. |
| alt_sgmii_mode | 21 | rwNormal read/write | 0x0 | Alternative sgmii mode. If asserted with sgmii_mode in the network control register the ACK bit is driven before ability detect during transfer of status information from the PHY to the MAC. |
| ptp_unicast_ena | 20 | rwNormal read/write | 0x0 | Enable detection of unicast PTP unicast frames. |
| tx_lpi_en | 19 | rwNormal read/write | 0x0 | Enable LPI transmission when set LPI (low power idle) is immediately transmitted |
| flush_rx_pkt_pclk | 18 | rwNormal read/write | 0x0 | Flush the next packet from the external RX DPRAM. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory. Self clearing register. |
| transmit_pfc_priority_based_pause_frame | 17 | woWrite-only | 0x0 | Write a one to transmit PFC priority based pause frame. Takes the values stored in the Transmit PFC Pause Register. Self clearing register. |
| pfc_enable | 16 | rwNormal read/write | 0x0 | Enable PFC Priority Based Pause Reception capabilities. Setting this bit will enable PFC negotiation and recognition of priority based pause frames. |
| store_rx_ts | 15 | rwNormal read/write | 0x0 | Store receive time stamp to memory. Setting this bit to one will cause the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point. Set to zero for normal operation. |
| Reserved | 14:13 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| tx_pause_frame_zero | 12 | woWrite-only | 0x0 | Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted. Self clearing register. |
| tx_pause_frame_req | 11 | woWrite-only | 0x0 | Transmit pause frame - writing one to this bit causes a pause frame to be transmitted. Self clearing register. |
| tx_halt_pclk | 10 | rwNormal read/write | 0x0 | Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends. Self clearing register. |
| tx_start_pclk | 9 | rwNormal read/write | 0x0 | Start transmission - writing one to this bit starts transmission. Self clearing register. |
| back_pressure | 8 | rwNormal read/write | 0x0 | Back pressure if set in 10M or 100M half duplex mode will force collisions on all received frames. Ignored in gigabit half duplex mode. |
| stats_write_en | 7 | rwNormal read/write | 0x0 | Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes. |
| inc_all_stats_regs | 6 | rwNormal read/write | 0x0 | Incremental statistics registers - this bit is write only. Writing a one increments all the statistics registers by one for test purposes. Self clearing register. |
| clear_all_stats_regs | 5 | rwNormal read/write | 0x0 | Clear statistics registers - this bit is write only. Writing a one clears the statistics registers. Self clearing register. |
| man_port_en | 4 | rwNormal read/write | 0x0 | Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low. |
| enable_transmit | 3 | rwNormal read/write | 0x0 | Transmit enable - when set, it enables the GEM transmitter to send data. When reset transmission will stop immediately, the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to point to the start of the transmit descriptor list. |
| enable_receive | 2 | rwNormal read/write | 0x0 | Receive enable - when set, it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer register is unaffected. |
| loopback_local | 1 | rwNormal read/write | 0x0 | Loopback local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd, tx_en to rx_dv and forces full duplex mode. Bit 11 of the network configuration register must be set low to disable TBI mode when in internal loopback. rx_clk and tx_clk may malfunction as the GEM is switched into and out of internal loopback. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loopback. Local loopback functionality is optional and may not be supported by some instantiations of the GEM. |
| loopback | 0 | rwNormal read/write | 0x0 | Reserved (loopback output signal is not implemented) |