pcap_status (CSU) Register Description
| Register Name | pcap_status |
|---|---|
| Offset Address | 0x0000003010 |
| Absolute Address | 0x00FFCA3010 (CSU) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000003 |
| Description | PCAP Status |
pcap_status (CSU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 28:14 | roRead-only | 0x0 | Reserved |
| pcfg_gwe | 13 | roRead-only | 0x0 | PL global write enable |
| pcfg_mcap_mode | 12 | roRead-only | 0x0 | Idicantes that the MCAP is active on the PL CFG. |
| pl_gts_usr_b | 11 | roRead-only | 0x0 | Indicates that the PL IO are globally tri-stated under user control |
| pl_gts_cfg_b | 10 | roRead-only | 0x0 | Indicates that the PL IO are globally tri-stated under cfg control |
| pl_gpwrdwn_b | 9 | roRead-only | 0x0 | Indicates that the PL is in a power down state (PL controlled) |
| pl_ghigh_b | 8 | roRead-only | 0x0 | Indicates that the PL interconnect is being held high |
| pl_fst_cfg | 7 | roRead-only | 0x0 | Indicates that the PL has completed its first configuration |
| pl_cfg_reset_b | 6 | roRead-only | 0x0 | Indicates that the PL is under reset |
| pl_seu_error | 5 | roRead-only | 0x0 | Indicates that the PL has encouted and SEU error (feature must be enabled in the PL) |
| pl_eos | 4 | roRead-only | 0x0 | Indicates that the PL has reached the end of startup |
| pl_done | 3 | roRead-only | 0x0 | Indicates that the PL configuration is done (done pad) |
| pl_init | 2 | roRead-only | 0x0 | Indicates that the PL has completed its init sequence |
| pcap_rd_idle | 1 | roRead-only | 0x1 | Indicates that all reads from the PL have completed. This should be used in conjuction with the CSU DMA status to determine when the PL readback has completed. This bit is not valid when the PCAP is in reset. 0x1 - Idle 0x0 - Readback in progress |
| pcap_wr_idle | 0 | roRead-only | 0x1 | Indicates that all writes to the PL have completed. This should be used in conjunction with the CSU DMA status to indicate when a PCAP write cycle has fully finished. This bit is not valid when the PCAP is in reset. 0x1 - Idle 0x0 - Writing to PL in progress |