pcs_control (GEM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

pcs_control (GEM) Register Description

Register Namepcs_control
Offset Address0x0000000200
Absolute Address 0x00FF0B0200 (GEM0)
0x00FF0C0200 (GEM1)
0x00FF0D0200 (GEM2)
0x00FF0E0200 (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00001040
DescriptionNote:All PCS registers are defined in the IEEE 802.3 Standard. PCS Control RegisterThis register provides the main control functions with respect to the PCS.

pcs_control (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16roRead-only0x0Reserved. Set to zero.
pcs_software_reset15rwNormal read/write0x0PCS software reset - written by software to force the hardware logic into a reset state. This bit is self clearing. When reading this bit, logic 1 is returned until both the soft reset has completed and the PCS is enabled through the PCS select bit of the network configuration register. Writing logic 0 has no effect.
loopback_mode14rwNormal read/write0x0Loopback mode - the ewrap output pin of the GEM reflects this control bit, and can be used to select loopback mode in the PHY transceiver. 0: Loopback mode disabled. 1: Loopback mode enabled.
speed_select_bit_113roRead-only0x0Speed select bit 1 - combined with speed select [0] to indicate the speed of operation of the PCS. As the GEM PCS is only intended to operate at 1000 Mbps, this bit is hardwired to logic 0.
enable_auto_neg12rwNormal read/write0x1Enable auto-negotiation - when set active high, auto-negotiation operation is enabled.
Reserved11:10roRead-only0x0Reserved. Set to zero.
restart_auto_neg 9rwNormal read/write0x0Restart auto-negotiation - when set active high, the hardware restarts auto-negotiation. This bit is self clearing, but once set shall remain in this state until auto-negotiation has restarted. Writing logic 0 has no effect.
mac_duplex_state 8roRead-only0x0MAC Duplex state. This returns the value of the MACs duplex state as indicated in bit 1 of the MACs network configuration register.
collision_test 7rwNormal read/write0x0Collision test - when set active high, the PCS generates collisions on transmit. This bit should only be set for test purposes.
speed_select_bit_0 6roRead-only0x1Speed select bit 0 - combined with speed select [1] to indicate the speed of operation of the PCS. As the GEM PCS is only intended to operate at 1000 Mbps, this bit is hardwired to logic 1.
Reserved 5:0roRead-only0x0Reserved. Set to zero.