phy_management (GEM) Register Description
| Register Name | phy_management |
|---|---|
| Offset Address | 0x0000000034 |
| Absolute Address |
0x00FF0B0034 (GEM0) 0x00FF0C0034 (GEM1) 0x00FF0D0034 (GEM2) 0x00FF0E0034 (GEM3) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 125 LPD_LSBUS_CLK clock cycles to complete, when MDC is set for LPD_LSBUS_CLK divide by 2 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. For a description of MDC generation, see Network Configuration Register. |
phy_management (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| write0 | 31 | rwNormal read/write | 0x0 | Must be written with 0. |
| write1 | 30 | rwNormal read/write | 0x0 | Must be written to 1 for a valid Clause 22 frame(0 for a valid Clause 45 frame). |
| operation | 29:28 | rwNormal read/write | 0x0 | Operation. For a Clause 45 frame: 00 is an addr, 01 is a write, 10 is a post read increment, 11 is a read frame. For a Clause 22 frame: 10 is a read, 01 is a write. |
| phy_address | 27:23 | rwNormal read/write | 0x0 | PHY address. |
| register_address | 22:18 | rwNormal read/write | 0x0 | Register address - specifies the register in the PHY to access. |
| write10 | 17:16 | rwNormal read/write | 0x0 | Must be written with 10. |
| phy_write_read_data | 15:0 | rwNormal read/write | 0x0 | For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. |