puf_shut (CSU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

puf_shut (CSU) Register Description

Register Namepuf_shut
Offset Address0x000000400C
Absolute Address 0x00FFCA400C (CSU)
Width32
TyperwNormal read/write
Reset Value0x01000020
DescriptionPUF Configuration 2

puf_shut (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
soset31:24rwNormal read/write0x1Shutter Offset Time.
Program this vlaue to 0x01.
sopen23:0rwNormal read/write0x20Shutter Open Time
SOPEN * 16 is the number of PUF clock cycles (200MHz +/-10%) where the "shutter" is open. The oscillator values can be captured only while the "shutter" is open. The minimum valud to program is 0x20, which means that each PUF oscillator is on for 32 PUF clock cycles. A starting recommneded value is between 10us and 40us. The four least significant bits are ignored
This should be programmed to 0x0005E, and might be adjusted depending on overflow conditions in STATUS register.