puf_tm_sw (CSU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

puf_tm_sw (CSU) Register Description

Register Namepuf_tm_sw
Offset Address0x0000004810
Absolute Address 0x00FFCA4810 (CSU)
Width32
TyperwNormal read/write
Reset Value0x01000020
DescriptionPUF Testmode 1 Sample Window

puf_tm_sw (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
OFF31:24rwNormal read/write0x1Offset.
Program to 0x01. This is the number of cycles from the start of the PUF oscillator oscillating to ignore (to help oscillator settle), expressed in number of 16 APB clock cycles. A 0x1 value means that during the first 16 APB clock cycles when the oscillator is oscillating, the oscillations are ignored.
SW23:0rwNormal read/write0x20Sample window register.
This is the number of cycles that each PUF oscillator is oscillating, expressed in number of APB clock cycles (nominally 200MHz in an ASIC implementation). The minimum value to program is 0x20, which means that each PUF oscillator is on for 32 APB clock cycles. A starting recommended value is 10us to 40us. The four lwast significant bits 3:0 are ignored.